APPLICATION SPECIFIC INTEGRATED CIRCUITS (ASICs)
Features matching the specific needs of the country
- CMOS Digital Process
- Gate length of 1.0 micron / Leff of 0.8 micron
- Metal pitch of 3.0 micron for both metal 1 and metal 2
- 5 Volts power supply
- Two levels of metal interconnects
- Planarization of interconnect levels
Well – proven library performance guarantees targeted specifications
- Typical gate delay of 156 ps
- Library contains more than 130 core cells
- Compiled Mega Cells
Comprehensive design support ensures early product realisation
- Cell based designs upto 1,00,000 gates
- Customised designs of much larger gate counts
- Design support options
- Full Contract design starting from Functional description
- Shares design starting from Layout stage
- Full "Customer" design (Upto GDS II tape stage)
- Auto test vector generation capability
- Die sizes upto 14 mm X 14 mm
- Typical pad pitch of 130 micron
No compromise on final Quality
- Entire Wafer fabrication in class 10 environment
- Exhaustive Process Control Monitors to guarantee performance
- Statistical Process Control in all stages of Wafer fabrication processes
- Process equipment tuning and calibration through trend charts
Applications to meet wide range of customer requirements
The technology is suitable for broad range of end products viz., Processors, Controllers, Data compression chips and Interface applications
- Complex digital designs
- High performance innovative designs
- Designs involving large die sizes
- Designs requiring optimization of standard functions with customized blocks / customized designs
- Low and medium production volumes
Packaging to suit customer / system specific needs
- Limited in-house capability towards fast prototyping services
- Supports industry standard packages as well as custom packages
Testing to ensure targeted performance
- Supports comprehensive testing
|
|
